High performance CMOS technology has been developed for years. In order to achieve high packing density wafer for ultra large scale integrated (ULSI) circuits, the dimensions of devices are scaled down to sub-micron range. The pay for the scaled devices is, for example, the parasitic effect which will degrade the RC delay and source and drain series resistance. Prior art discloses the degradation factor of propagation delay (Tpd) on gate electrode sheet resistance (Rgsh) as function of channel width. Please refer to the article "A Novel 0.15 .mu.m CMOS Technology using W/WN.sub.X /Polysilicon Gate Electrode and Ti Silicided Source/Drain Diffusions, M. T. Takagi et al., 1996, IEDM 96-455". The author suggests that the use of lower Rgsh enlarges the degree of freedom in LSI design. Self-aligned metal silicided process is one of the way to reduce the resistance of the gate, the source and drain. In addition, the self-aligned metal silicided process can increase the operation speed, which is a requirement for ultra-short channel MOSFET. CMOS technology integrating W/WN.sub.X /Polysilicon gate electrode and Ti silicided source and drain has been proposed by Takagi.
For ULSI circuits, the gate oxide is also shrink to a very thin dimension. Therefore, the reliability of the ultra thin oxide is a serious problem to the scaled devices. Typically, the reliability of the gate oxide is influenced by many factors, such as the hot carriers and the radiation hardness. In order to provide MOSFETs with reliable gate oxide, many structure of the gate oxide have been proposed. For example, the oxide containing nitrogen atoms is used to take place of the thermal oxide. Another method is the use of fluorinated gate oxides that are formed by immersing silicon in HF solution or by ion implantation of F atoms into silicon gate. One prior art to approach the purpose is by forming a liquid phase deposition (LPD) oxide followed by a high temperature rapid thermal oxidation in oxygen or N.sub.2 O ambient. The F atoms will be incorporated into the oxides by LPD technique. Please see "Reliable Fluorinated Thin Gate Oxides Prepared by Liquid Phase Deposition Following Rapid Thermal Process, Wei-Shin Lu, 1996, IEEE". In the method, the F and N atoms can be simultaneously incorporated into the oxide.
An article relating to the LPD is the literature "The Physicochemical Properties and Growth Mechanism of Oxide (SiO.sub.2-X F.sub.X) by Liquid Phase Deposition with H.sub.2 O Addition Only, Ching-Fa Yeh, J. Electrochem. Soc., Vol. 141, No. 11, 1994". The oxide can be formed at room temperature by using liquid phase deposition technology, which is referred to the LPD-oxide. The LPD-oxide can be formed by adding H.sub.3 BO.sub.3 or Al to hydrofluosilicic acid (H.sub.2 SiF.sub.6) solution. Equations 1 and 2 below describe the reactions. EQU H.sub.2 SiF.sub.6 +2H.sub.2 O.rarw..fwdarw.6HF+SiO.sub.2 (1) EQU H.sub.3 BO.sub.3 +4HF.rarw..fwdarw.BF.sub.4.sup.- +H.sub.3 O.sup.+ +2H.sub.2 O (2)
To precisely control the impurity distribution is another issue of the scaled devices. Shallow and high concentration p source and drain is a requirement for ULSI PMOS. It is very hard to obtain the aforementioned condition by using ion implantation. A solid phase diffusion (SPD) has been proposed to overcome the issue. More detail, the shallow source and drain of the PMOS are formed by SPD from boron-silicate glass, without affecting the NMOS (See "High Performance Sub-Tenth Micron CMOS Using Advanced Boron Doping and Wsi.sub.2 Dual Gate Process, Takeuchi, 1995 Symposium on VLSI Technology Digest of Technique Papers").
However, the conventional method to form CMOS devices needs a lot of mask. Thus, the present invention provides a method for forming CMOS devices with reducing the number of mask.